How are you going to generate USB traffic? FTDI's libftd2xx works fine under Windows and Linux. The CLKOUT signal is the clock given to me from the FTDI (60MHz). I'm using a FT2232H in synchronous mode, since this is the fastest transfer option for data (high data throughput is needed for the purpose of the whole design - in both directions). Thank's in advance for any help You can give me, The sample 0x4e should be written to the FIFO only once, but when I request it, the output of the FIFO does not change from 0x4e to 0x4f, as I would expect.Īm I doing something wrong? Is there some special case with contolling the FIFO I've missed to take into account in my design? However, this didn't change the FIFOs behaviour.

In the attached picture You can see the FIFO input domain (clkSystem is 100MHz, both the logic and the FIFO work on the raising clock edge) in green colour, and the FIFO output domain (CLKOUT is 60MHz, control logic works on the rising edge, FIFO on the falling edge) in light blue.Īlso, the write request signal runs through an AND gate, combined with the inverted FIFO full signal (this isn't usually the case in my design - I added this to make sure the sample isn't written twice). It has write on full / read on empty protection enabled.Įverything seems to work well except for a special situation in which either the writing or reading of a sample does not work (sample is either written twice, or read twice - I don't know). The FIFO I'm using has a sample depths of 8 samples (in order to test wether my design handles FIFO full / empty signals correctly). I attached a picture of the functiuonal simulation, created with Quartus 10.1 (SP1) and Modelsim 6.6c. Yesterday I encountered a strange problem when simulating a DCFIFO (Altera Megafunction).

Wireshark usb ftdi